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1 features ? 16m bit (1m x 16) flash memory ? 3.0 10% read/write ? random access time - 100 ns ? burst access time - 25 ns ? sector erase architecture C thirty 32k word (64k byte) sectors with individual write lockout C two 16k word (32k byte) sectors with individual write lockout C eight 4k word (8k byte) sectors with individual write lockout ? typical word programming time - 30 s ? typical sector erase time: 32k word sectors - 500 ms; 4k word sectors - 100 ms ? dual plane organization, permitting concurrent read while program/erase C memory plane a: eight 4k word, two 16k word and six 32k word sectors C memory plane b: twenty-four 32k word sectors ? erase suspend capability C supports reading/programming data from any sector by suspending erase of any different sector ? low-power operation C 30 ma active C 10 a standby ? data polling and toggle bit for end of program detection ? optional vpp pin for fast programming ? reset input for device initialization ? tsop and bga package product description the AT49BN1604(t) is a 2.7 volt 16-megabit flash memory. the memory is divided into 40 blocks for erase operations. its synchronous architecture allows fast sequen- tial burst accesses of 25 ns after an initial random access of 100 ns. this device can be read or reprogrammed off a single 2.7v power supply, making it ideally suited for 16-megabit (1m x 16) burst mode 3-volt only flash memory AT49BN1604 AT49BN1604t advance information rev. 1141bC05/99 pin configurations pin name pin function i/o0-i/o15 data inputs/outputs a0-a19 addresses ce chip enable oe output enable we write enable avd address latch enable baa advance clk clock reset reset vpp optional power supply for faster program/ erase operations vccq output power supply rdy ready dc dont connect (continued)
AT49BN1604(t) 2 in-system programming. the output voltage can be sepa- rately controlled down to 1.65v through the vccq supply pin. the device is segmented into two memory planes. reads from memory plane b may be performed even while pro- gram or erase functions are being executed in memory plane a and vice versa. this operation allows improved system performance by not requiring the system to wait for a program or erase operation to complete before a read is performed. to further increase the flexibility of the device, it contains an erase suspend feature. this feature will put the erase on hold for any amount of time and let the user read data from or program data to any of the remaining sectors. the end of program or erase is detected by data polling, or toggle bit. a v pp pin is provided to improve program/erase times. this pin does not need to be utilized. if it is not used the pin should be connected to ground. to take advantage of faster programming, the pin should supply 4.5 to 5.5 volts during program and erase operations. with v pp at 5v, a six byte command to remove the require- ment of entering the three byte program sequence is offered to further improve programming time. after entering the six byte code, only single pulses on the write control lines are required for writing into the device. this mode is exited by powering down the device, by taking the reset pin to gnd or by a high to low transition on the v pp input. this mode is not exited by the read reset command. erase, erase suspend/resume and read reset commands will not work while in this mode; if entered they will result in data being programmed into the device. it is not recom- mended that the six byte code reside in the software of the final product but only exist in external programming code. device operation random read: the random read operation of the device is controlled by ce , oe , and avd inputs. the outputs are put in the high impedance state whenever ce or oe is high. this dual-line control gives designers flexibility in pre- venting bus contention. the data at the address location defined by a0-a19 and captured by the avd signal will be read when ce and oe are low. the address location passes into the device when ce and avd are low; the address is latched on the low to high transition of avd . low input levels on the oe and ce pins allow the data to be driven out of the device. the access time is measured from stable address, falling edge of avd or falling edge of ce , whichever occurs last. the baa signal must be held high, and no clock signal is provided during random reads. burst read: the burst read operation of the device is controlled by ce , oe , clk, baa and avd inputs. the initial read location is determined as for the random read opera- tion; it can be any memory location in the device. a low input on the baa signal indicates that a burst read will occur. in the burst access, the address is latched on the ris- ing edge of the first clock pulse when avd is low or the ris- tsop to p v i e w 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 vccq rdy nc a16 a15 a14 a13 a12 a11 gnd avd clk dc vcc we reset vpp a19 a18 a17 a10 a9 a8 a7 a6 ce baa gnd nc gnd i/o15 i/o7 i/o14 i/o6 gnd i/o13 i/o5 i/o12 i/o4 i/o11 i/o3 i/o10 i/o2 vccq i/o9 i/o1 i/o8 i/o0 a5 a4 a3 a2 a1 a0 oe nc bga top view a b c d e f 1 2345678910 nc vss baa a1 a0 oe ce a6 a7 a4 a3 a2 a8 a9 a10 i/o8 i/o0 a5 a17 a18 a19 nc i/o9 i/o1 vpp reset nc nc i/o2 vccq vcc we dc nc i/o10 i/o3 avd clk vss i/o11 i/o4 i/o12 a12 a11 a13 i/o5 i/o13 vss a15 a14 a16 nc i/o6 i/o14 vccq rdy nc i/o7 i/o15 vss
AT49BN1604(t) 3 ing edge of the avd signal whichever occurs first. the clk signal controls the flow of data from the device for a burst operation. to perform a burst read, the baa signal should go low during the clock cycle prior to the beginning of the burst. when the baa signal is low, the data at the next sequential address in memory is read for each following clock cycle. during a given burst mode read, any number of addresses can be read from the memory. when a page boundary in the memory is transitioned, additional time may be required for the device to continue the burst read. to indicate that it is not ready to continue the burst, the device will drive the rdy pin low during the clock cycles in which new data is not being presented. once the rdy pin is driven high, the next data will be valid. starting with address zero, page boundaries occur every 128 words in the memory. during the burst mode, depending on the initial address that is read, the first page boundary transition may occur before 128 words are read. the rdy signal will be tri-stated when the ce or oe signal is high. in the burst read cycle waveform as shown on page 13, the data d0 is valid asynchronously from point a, the point when the addresses are latched. the low to high transition of the clock at point b results in no change of data because the rdy signal is low. the low to high transition of the clock at point c results in the first burst word, d1, being read. the transition of the clock at point d results in a burst read of the last word of the page, d127. the clock transi- tion at point e does not cause new data to appear on the output lines because the rdy signal goes low after the clock transition which signifies that a page boundary in the memory has been crossed and that new data is not avail- able. the clock transition at point f does cause a burst read of data d128 because the rdy signal goes high after the clock transition indicating that new data is available. as long as the baa signal is low, additional clock transitions, like at point g, will continue to result in burst reads until the next page boundary is crossed between word d255 and d256. command sequences: the device powers on in the read mode. command sequences are used to place the device in other operating modes such as program and erase. the command sequences are written by applying a low pulse on the we input with ce low and oe high. prior to the low going pulse on the we signal, the address input must be latched by a low to high transition on the avd sig- nal. valid data is asserted when the we signal is low and latched on the rising edge of the we pulse. the addresses used in the command sequences are not affected by enter- ing the command sequences. reset: a reset input pin is provided to ease some sys- tem applications. when reset is at a logic high level, the device is in its standard operating mode. a low level on the reset pin halts the present device operation and puts the outputs of the device in a high impedance state. when a high level is reasserted on the reset pin, the device returns to read or standby mode, depending upon the state of the control pins. by applying a 12 0.5v input sig- nal on the reset pin any sector can be reprogrammed even if the sector lockout feature has been enabled. erase: before a word can be reprogrammed it must be erased. the erased state of the memory bits is a logical 1. the entire memory can be erased by using the chip erase command or individual sectors can be erased by using the sector erase commands. chip erase: chip erase is a six bus cycle operation. the automatic erase begins on the rising edge of the last we pulse. chip erase does not alter the data of the protected sectors. after the full chip erase the device will return back to the read mode. the hardware reset during chip erase will stop the erase but the data will be of unknown state. any command during chip erase except erase suspend will be ignored. sector erase: as an alternative to a full chip erase, the device is organized into 40 sectors that can be individually erased. the sector erase command is a six bus cycle operation. the sector whose address is valid at the sixth falling edge of we will be erased provided the given sector has not been protected. word programming: the device is programmed on a word by word basis. programming is accomplished via the internal device command register and is a four bus cycle operation. the programming address and data are latched in the fourth cycle. the device will automatically generate the required internal programming pulses. please note that a 0 cannot be programmed back to a 1; only erase oper- ations can convert 0s to 1s. during the programming mode, the clock signal must be held low or high and cannot toggle. sector programming lockout: each sector has a programming lockout feature. this feature prevents pro- gramming of data in the designated sectors once the fea- ture has been enabled. the sectors that are locked out can contain secure code that can bring up the system. enabling the lockout feature will allow the boot code to stay in the device while data in the rest of the memory is updated. this feature does not have to be activated; any sectors usage as a write protected region is optional to the user. once the feature is enabled, the data in the protected sector can no longer be erased or programmed when input levels of 5.5v or less are used. data in the remaining sectors can still be changed through the regular programming method. to acti- vate the lockout feature, a series of six program commands to specific addresses with specific data must be performed. sector lockout detection: a software method is available to determine if programming of a sector is locked out. when the device is in the software product identifica-
AT49BN1604(t) 4 tion mode (see software product identification entry and exit sections) a read from address location 00002h within a sector will show if programming the sector is locked out. if the data on i/o0 is low, the sector can be programmed; if the data on i/o0 is high, the program lockout feature has been enabled and the sector cannot be programmed. the software product identification exit code should be used to return to standard operation. sector programming lockout override: the user can override the sector programming lockout by taking the reset pin to 12v 0.5 volts. by doing this protected data can be altered through a chip erase, sector erase or word programming. when the reset pin is brought back to ttl levels, the sector programming lockout feature is again active. data polling: the AT49BN1604(t) features data poll- ing to indicate the end of a program cycle. during a pro- gram cycle an attempted read of the last word loaded will result in the complement of the loaded data on i/o7. once the program or erase cycle has been completed, true data will be read from the device. data bar polling may begin at any time during the program cycle. please see status bit table on page 18 for more details. toggle bit: in addition to data bar polling the AT49BN1604(t) provides another method for determining the end of a program or erase cycle. during a program or erase operation, successive attempts to read data from the device will result in i/o6 toggling between a 1 and 0. once the program cycle has completed, i/o6 will stop tog- gling and valid data will be read. examining the toggle bit may begin at any time during a program cycle. an additional toggle bit is available on i/o2 which can be used in conjunction with the toggle bit which is available on i/o6. while a sector is erase suspended, a read or a pro- gram operation from the suspended sector will result in the i/o2 bit toggling. please see status bit table on page 18 for more details. erase suspend/resume: the erase suspend allows the user to interrupt a sector erase operation and then per- form a data read on the remaining sectors. this feature is only allowed during the sector erase operation. the device will take up to a maximum of 20 s to suspend the erase. to resume the erase operation, the erase resume com- mand sequence should be written to the device. the sector erase operation will then continue. another erase suspend command can be written after the chip has resumed eras- ing. hardware data protection: hardware features protect against inadvertent programs to the AT49BN1604(t) in the following ways: (a) v cc sense: if v cc is below 1.8v (typical), the program function is inhib- ited. (b) v cc power on delay: once v cc has reached the v cc sense level, the device will automatically time out 10 ms (typical) before programming. (c) program inhibit: hold- ing any one of oe low, ce high or we high inhibits pro- gram cycles. (d) noise filter: pulses of less than 15 ns (typical) on the we or ce inputs will not initiate a program cycle. input levels: while operating with a 2.7v to 3.3v power supply, the address inputs and control inputs (oe , ce , and we ) may be driven from 0 to 5.5v without adversely affecting the operation of the device. the i/o lines can only be driven from 0 to v ccq + 0.6v. output levels: output high levels (v oh ) are equal to v ccq - 0.1v (not v cc ). for 2.7v - 3.3v output levels, v ccq must be tied to v cc . for 1.65v - 2.2v output levels, v ccq must be regulated to 2.0v 10% while v cc must be regu- lated to 2.7v - 3.0v (for minimum power).
AT49BN1604(t) 5 notes: 1. the data format in each bus cycle is as follows: i/o15 - i/o8 (dont care); i/o7 - i/o0 (hex). the address format in each bus cycle is as follows: a15 - a0 (hex), a14 - a19 (dont care). 2. either one of the product id exit commands can be used. 3. sa = sector address. any word address within a sector can be used to designate the sector address (see next four pages for details). 4. when the sector programming lockout feature is not enabled, the sector will erase (from the same sector erase command). once the sector has been protected, data in the protected sectors cannot be changed unless the reset pin is taken to 12v 0.5v. 5. pa is the plane address (a19 - a18). command definition in hex (1) command sequence bus cycles 1st bus cycle 2nd bus cycle 3rd bus cycle 4th bus cycle 5th bus cycle 6th bus cycle addr data addr data addr data addr data addr data addr data read 1 addr d out chip erase 6 5555 aa 2aaa 55 5555 80 5555 aa 2aaa 55 5555 10 sector erase 6 5555 aa 2aaa 55 5555 80 5555 aa 2aaa 55 sa (3)(4) 30 word program 4 5555 aa 2aaa 55 5555 a0 addr d in bypass unlock 6 5555 aa 2aaa 55 5555 80 5555 aa 2aaa 55 5555 a0 single pulse word program 1 addr d in sector lockout 6 5555 aa 2aaa 55 5555 80 5555 aa 2aaa 55 sa (3)(4) 40 erase suspend 1 xxxx b0 erase resume 1 pa (5) 30 product id entry 3 5555 aa 2aaa 55 5555 90 product id exit (2) 3 5555 aa 2aaa 55 5555 f0 product id exit (2) 1 xxxx f0 absolute maximum ratings* temperature under bias................................ -55c to +125c *notice: stresses beyond those listed under absolute maximum ratings may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature ..................................... -65c to +150c all input voltages (including nc pins) with respect to ground ...................................-0.6v to +6.25v all output voltages with respect to ground .............................-0.6v to v cc + 0.6v voltage on oe with respect to ground ...................................-0.6v to +13.5v
AT49BN1604(t) 6 AT49BN1604 memory plane a - bottom boot sector size (words) address range (a19 - a0) sa0 4k 00000 - 00fff sa1 4k 01000 - 01fff sa2 4k 02000 - 02fff sa3 4k 03000 - 03fff sa4 4k 04000 - 04fff sa5 4k 05000 - 05fff sa6 4k 06000 - 06fff sa7 4k 07000 - 07fff sa8 16k 08000 - 0bfff sa9 16k 0c000 - 0ffff sa10 32k 10000 - 17fff sa11 32k 18000 - 1ffff sa12 32k 20000 - 27fff sa13 32k 28000 - 2ffff sa14 32k 30000 - 37fff sa15 32k 38000 - 3ffff
AT49BN1604(t) 7 AT49BN1604 memory plane b - bottom boot sector size (words) address range (a19 - a0) sa16 32k 40000 - 47fff sa17 32k 48000 - 4ffff sa18 32k 50000 - 57fff sa19 32k 58000 - 5ffff sa20 32k 60000 - 67fff sa21 32k 68000 - 6ffff sa22 32k 70000 - 77fff sa23 32k 78000 - 7ffff sa24 32k 80000 - 87fff sa25 32k 88000 - 8ffff sa26 32k 90000 - 97fff sa27 32k 98000 - 9ffff sa28 32k a0000 - a7fff sa29 32k a8000 - affff sa30 32k b0000 - b7fff sa31 32k b8000 - bffff sa32 32k c0000 - c7fff sa33 32k c8000 - cffff sa34 32k d0000 - d7fff sa35 32k d8000 - dffff sa36 32k e0000 - e7fff sa37 32k e8000 - effff sa38 32k f0000 - f7fff sa39 32k f8000 - fffff
AT49BN1604(t) 8 AT49BN1604t memory plane b - top boot sector size (words) address range (a19 - a0) sa0 32k 00000 - 07fff sa1 32k 08000 - 0ffff sa2 32k 10000 - 17fff sa3 32k 18000 - 1ffff sa4 32k 20000 - 27fff sa5 32k 28000 - 2ffff sa6 32k 30000 - 37fff sa7 32k 38000 - 3ffff sa8 32k 40000 - 47fff sa9 32k 48000 - 4ffff sa10 32k 50000 - 57fff sa11 32k 58000 - 5ffff sa12 32k 60000 - 67fff sa13 32k 68000 - 6ffff sa14 32k 70000 - 77fff sa15 32k 78000 - 7ffff sa16 32k 80000 - 87fff sa17 32k 88000 - 8ffff sa18 32k 90000 - 97fff sa19 32k 98000 - 9ffff sa20 32k a0000 - a7fff sa21 32k a8000 - affff sa22 32k b0000 - b7fff sa23 32k b8000 - bffff
AT49BN1604(t) 9 AT49BN1604t memory plane a - top boot sector size (words) address range (a19 - a0) sa24 32k c0000 - c7fff sa25 32k c8000 - cffff sa26 32k d0000 - d7fff sa27 32k d8000 - dffff sa28 32k e0000 - e7fff sa29 32k e8000 - effff sa30 16k f0000 - f3fff sa31 16k f4000 - f7fff sa32 4k f8000 - f8fff sa33 4k f9000 - f9fff sa34 4k fa000 - fafff sa35 4k fb000 - fbfff sa36 4k fc000 - fcfff sa37 4k fd000 - fdfff sa38 4k fe000 - fefff sa39 4k ff000 - fffff
AT49BN1604(t) 10 notes: 1. x can be v il or v ih . 2. refer to ac programming waveforms. 3. v h = 12.0v 0.5v. 4. manufacturer code: 001fh, device code: 00dfhCAT49BN1604, 00dehCAT49BN1604t. 5. see details under software product identification entry/exit. 6. the use of the vpp pin is optional. note: 1. in the erase mode, i cc is 30 ma. dc and ac operating range AT49BN1604(t)-10 operating temperature (case) com. 0c - 70c ind. -40c - 85c v cc power supply 2.7v to 3.3v operating modes mode ce oe we reset baa v pp (6) ai i/o read v il v il v ih v ih v ih xaid out burst read v il v il v ih v ih v il xaid out program/erase (2) v il v ih v il v ih v ih 5v 10% ai d in standby/program inhibit v ih x (1) xv ih x x x high z program inhibit x x v ih v ih v ih x program inhibit x v il xv ih v ih x output disable x v ih xv ih x x high z reset x x x v il v ih x x high z product identification hardware v il v il v ih v ih v ih a1 - a19 = v il , a9 = v h (3), , a0 = v il manufacturer code (4) a1 - a19 = v il , a9 = v h (3) , a0 = v ih device code (4) software (5) v ih a0 = v il , a1 - a19 = v il manufacturer code (4) a0 = v ih , a1 - a19 = v il device code (4) dc characteristics symbol parameter condition min max units i li input load current v in = 0v to v ccq 10 m a i lo output leakage current v i/o = 0v to v ccq 10 m a i sb1 v cc standby current cmos ce = v ccq - 0.3v to v ccq 10 m a i sb2 v cc standby current ttl ce = 2.0v to v ccq 1ma i cc (1) v cc active current f = 40 mhz; i out = 0 ma 30 ma i ccre v cc read while erase current f = 40 mhz; i out = 0 ma 50 ma i ccrw v cc read while write current f = 40 mhz; i out = 0 ma 50 ma v il input low voltage 0.6 v v ih input high voltage v ccq = 1.65v - 2.2v v ccq - 0.2 v v ccq = 2.7v - 3.3v 2.0 v ol output low voltage i ol = 2.1 ma 0.45 v v oh output high voltage i oh = -100 a; v ccq = 1.65v - 2.2v v ccq - 0.1 v i oh = -400 a; v ccq = 2.7v - 3.3v 2.4
AT49BN1604(t) 11 random read cycle waveform input test waveforms and measurement level t r , t f < 5 ns output test load note: 1. this parameter is characterized and is not 100% tested. ac random read timing characteristics symbol parameter min. max. units t acc1 access, avd to data valid 100 ns t acc2 access, address to data valid 100 ns t acc3 access, ce to data valid 100 ns t oe oe to data valid 25 ns t ahav address hold from avd 0ns t avlp avd low pulsewidth 25 ns t avhp avd high pulsewidth 25 ns t aav address valid to avd 15 ns t df ce , oe high to data float 25 ns t ro reset to output delay 800 ns t acc3 t acc2 t df t df t ahav t avlp t acc1 data valid ce i/o0-i/o15 a0 -a19 avd oe t aav t oe t avhp reset t ro 30 pin capacitance f = 1 mhz, t = 25c (1) typ max units conditions c in 46 pfv in = 0v c out 812 pfv out = 0v
AT49BN1604(t) 12 burst read cycle waveform ac burst read timing characteristics symbol parameter min. max. units t clk clk period 25 ns t ckh clk high time 7 ns t ckl clk low time 7 ns t ckrt clk rise time 5ns t ckft clk fall time 5ns t ack address valid to clock 7 ns t avck avd low to clock 7 ns t ceck ce low to clock 7 ns t qhck output hold from clock 3 ns t ahck address hold from clock 10 ns t ckry clock to rdy delay 20 ns t back baa setup to clock 7 ns t ceav ce setup to avd 25 ns t aav address valid to avd 15 ns t ahav address hold from avd 10 ns t ckqv clk to data delay 20 ns t ceqz ce high to output high z 25 ns t bbt burst busy time 150 ns d0 d127 d1 d128 ce i/o0-i/o15 a0-a19 avd clk oe baa t clk t ckh t ckl ... rdy t ceav t acc3 t ahav t aav d129 ... d126 ... t ceck t ahck t avck t ack t bbt t ckry t ckry t ckqv t ceqz t qhck t back
AT49BN1604(t) 13 burst read cycle waveform d0 d127 d1 d128 ce i/o0-i/o15 a0 -a19 avd clk oe baa rdy d129 ... d126 ... ... a c d e f g b
AT49BN1604(t) 14 ac word load waveforms we controlled ce controlled ac word load characteristics symbol parameter min. max. units t as address, ce setup time to avd high 15 ns t ahav address hold time 10 ns t avlp avd low pulsewidth 25 ns t ds data setup time 15 ns t dh data hold time 0 ns t ceav ce setup to avd 25 ns t wp ce or we low pulsewidth 100 ns t ds t dh t as t ahav t avlp t wp data valid ce i/o0-i/o15 a0 -a19 avd we clk t ds t dh t as t ahav t avlp t wp data valid ce i/o0-i/o15 a0 -a19 avd we t ceav clk
AT49BN1604(t) 15 program cycle waveforms sector or chip erase cycle waveforms notes: 1. oe must be high only when we and ce are both low. 2. for chip erase, the address should be 5555. for sector erase, the address depends on what sector is to be erased. (see note 3 under command definitions.) 3. for chip erase, the data should be xx10h, and for sector erase, the data should be xx30h. program cycle characteristics symbol parameter min typ max units t bp word programming time 30 50 m s t as address set-up time 15 ns t ahav address hold time 10 ns t ds data set-up time 15 ns t dh data hold time 0 ns t wp write pulse width 100 ns t wph write pulse width high 50 ns t sec1 sector erase cycle time (4k word sectors) 100 ms t sec2 sector erase cycle time (32k word sectors) 500 ms t ec chip erase cycle time 10 seconds input data xxaa ce we i/o0 -i/o15 xx55 xxa0 a0 -a19 avd addr 5555 2aaa 5555 oe (1) clk oe (1) xxaa xxaa ce we i/o0 -i/o15 xx55 xx80 a0 -a19 avd 5555 5555 2aaa 5555 xx55 note3 2aaa note2 clk
AT49BN1604(t) 16 notes: 1. these parameters are characterized and not 100% tested. 2. see t oe spec in ac read characteristics. data polling waveforms notes: 1. these parameters are characterized and not 100% tested. 2. see t oe spec in ac read characteristics. toggle bit waveforms (1)(2)(3) notes: 1. toggling either oe or ce or both oe and ce will operate toggle bit. the t oehp specification must be met by the toggling input(s). 2. beginning and ending state of i/o6 will vary. 3. any address location may be used but the address should not vary. data polling characteristics symbol parameter min typ max units t dh data hold time 10 ns t oeh oe hold time 10 ns t oe oe to output delay (2) ns t wr write recovery time 0 ns toggle bit characteristics (1) symbol parameter min typ max units t dh data hold time 10 ns t oeh oe hold time 10 ns t oe oe to output delay (2) ns t oehp oe high pulse 150 ns t wr write recovery time 0 ns
AT49BN1604(t) 17 software product identification entry (1) software product identification exit (1)(6) notes: 1. data format: i/o15 - i/o8 (dont care); i/o7 - i/o0 (hex) address format: a15 - a0 (hex), a15 - a19 (dont care). 2. a1 - a19 = v il . manufacture code is read for a0 = v il ; device code is read for a0 = v ih . 3. the device does not remain in identification mode if powered down. 4. the device returns to standard operation mode. 5. manufacturer code: 001fh device code: 00dfhCAT49BN1604, 00dehCAT49BN1604t 6. either one of the product id exit commands can be used. sector lockout enable algorithm (1) notes: 1. data format: i/o15 - i/o8 (dont care); i/o7 - i/o0 (hex) address format: a15 - a0 (hex), a15 - a19 (dont care). 2. sector lockout feature enabled. load data aa to address 5555 load data 55 to address 2aaa load data 90 to address 5555 enter product identification mode (2)(3)(5) load data aa to address 5555 load data 55 to address 2aaa load data f0 to address 5555 exit product identification mode (4) or load data f0 to any address exit product identification mode (4) load data aa to address 5555 load data 55 to address 2aaa load data 80 to address 5555 load data aa to address 5555 load data 55 to address 2aaa load data 40 to address 5555 pause 1 second (2)
AT49BN1604(t) 18 status bit table status bit i/o 7 i/o 6 i/o 2 read address in plane a plane b plane a plane b plane a plane b while programming in plane a i/o7 data toggle data 1 data programming in plane b data i/o7 data toggle data 1 erasing in plane a 0 data toggle data toggle data erasing in plane b data 0 data toggle data toggle erase suspended & read erasing sector 1 1 1 1 toggle toggle erase suspended & read non-erasing sector data data data data data data erase suspended & program erasing sector 1 1 1 1 toggle toggle erase suspended & program non-erasing sector in plane a i/o7 data toggle data toggle data erase suspended & program non-erasing sector in plane b data i/o7 data toggle data toggle
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